1. Technical Field
This invention relates to the manufacture of VLSI semiconductor chips, boards and assemblies, and, more particularly, to a process for forming multi-level coplanar metal insulator films on a substrate.
2. Description of the Prior Art
In the field of VLSI semiconductor chip processing, multi-level metal patterns are used to interconnect devices. One technique for accomplishing this is disclosed in IBM Tech. Discl. Bull., Vol. 25, No. 10 (Mar. 1983), pp. 5309-5314, where a first metal pattern is formed in an insulator layer. An insulator layer is deposited, and a series of holes are etched through this layer in locations where interconnections (or stud vias) are desired. The holes are filled with metal, excess metal is lifted off, and another insulator layer is deposited; this layer is patterned, and metal is deposited in these openings, thus making contact with the first metal pattern. This process is cumbersome and costly to carry out, however, as it involves several sequences of masking and etching steps.
A simpler approach is shown in U.S. Pat. No. 4,789,648, issued to Chow, et al. on Dec. 6, 1988, which includes the following steps: depositing an insulator layer over an underlying insulator layer containing a metal pattern; applying an etch stop layer; defining holes in the etch stop; depositing another insulator layer; etching openings (or wiring channels) in the upper insulator layer in alignment with the holes in the etch stop, and continuing the etching into the first insulator layer to form via holes; overfilling the channels and via holes with metal; and then removing the excess metal to form a coplanar metal/insulator surface. While this process is less complicated than that disclosed in the article discussed above, nevertheless, it still involves two sequences of masking and etching steps to form the via holes and the wiring channels.
Another conventional technique, known as the pillar process, is exemplified in U.S. Pat. No. 4,621,045, issued to Goodner on Nov. 4, 1986, in which a conductive pillar is provided in an insulator layer to connect two layers of metal. This process also has a high degree of complexity, however, with multiple masking and etching sequences.